The performance of high-end microprocessors has continued to increase over the years. In some cases, this performance increase is associated with higher clock frequencies (and smaller clock periods), which tends to increase power consumption. Higher frequencies and higher power consumption can give rise to various issues in an integrated circuit and/or its packaging, which can tend to limit proper operation of the chip, and can contribute to eventual failure of the chip. More recently, techniques have been employed to mitigate these issues by dynamically changing the operating voltage and/or frequency of the chip.
One such technique is known as Dynamic Voltage Frequency Scaling (DVFS), with which the operating frequency and power supply of a chip can be adjusted at any time (asynchronously). For example, DVFS can be used to reduce power consumption by lowering the operating frequency of the chip when the chip is in a standby mode and/or other less active operating modes. DVFS and other techniques can involve adjusting operating frequencies by switching between two or more clock sources. Traditionally, the clock switching can introduce a glitch in the clock signal and/or long clock down times, particularly when asynchronous operation is desired. These types of glitches are potentially harmful to downstream circuitry, and long down times can introduce undesirable effects (e.g., voltage noise).